FIG. 40 is a circuit diagram illustrating a conventional shift register for use in a gate driver that is included in a liquid crystal display device. As shown in FIG. 40, a conventional shift register 100 is made up of a plurality of shift circuits (unit circuits) sc1, sc2, . . . scm, and scd, which are connected in stages. Each of the shift circuits sci (i=1, 2, 3, . . . or m) includes input nodes qfi, qbi, and CKAi, and an output node qoi. The shift circuit scd, which is a dummy shift circuit, includes input nodes qfd and CKAd and an output node qod.
The shift circuit sc1 has its node qf1 be connected to an output terminal via which a gate start pulse signal GSP is outputted, has its node qb1 be connected to the node qo2 of the shift circuit sc2, and has its node CKA1 be connected to a first clock line CKL1 to which a first clock signal is supplied; and from its node qo1, a gate on-pulse signal (signal line selection signal) g1 is outputted. Further, each of the shift circuits sci (i=2, 3, . . . or m−1) has its node qfi be connected to the node qo(i-1) of the shift circuit sc(i−1), has its node qbi be connected to the node qo(i+1) of the shift circuit sc(i+1), and has its node CKAi be connected to the first clock line CKL1 or a second clock line CKL2 to which a second clock signal is supplied; and from its node qoi, a gate on-pulse signal (signal line selection signal) gi is outputted. In a case where i is an odd number, the node CKAi is connected to the first clock line CKL1, and in a case where i is an even number, the node CKAi is connected to the second clock line CKL2.
The shift circuit scm has its node qfm be connected to the node qo(m−1) of the shift circuit sc(m−1), has its node qbm be connected to the node qod of the dummy shift circuit scd, and has its node CKAm be connected to the first clock line CKL1 or the second clock line CKL2; and from its node qom, the gate on-pulse signal (signal line selection signal) gm is outputted. In a case where m is an odd number, the shift circuit scm has its node CKAi be connected to the first clock line CKL1, and in a case where m is an even number, the shift circuit scm has its node CKAi be connected to the second clock line CKL2. The dummy shift circuit scd has its node qfd be connected to the node qom of the shift circuit scm, and its node CKAd be connected to the first clock line CKL1 or the second clock line CKL2. In the case where m is an odd number, the dummy shift circuit scd has its node CKAd be connected to the second clock line CKL2, and in the case where m is an even number, the dummy shift circuit scd has its node CKAd be connected to the first clock line CKL1.
FIG. 41 is a timing chart illustrating waveforms of a vertical sync signal VSYNC, the gate start pulse signal GSP, the first clock signal CK1, the second clock signal CK2, gate on-pulse signals gi (i=1 to m), and an output via the node qod. Note that each of the first clock signal CK1 and the second clock signal CK2 includes, in one cycle, one “H (high)” (active) clock period and one “L (low)” (non-active) clock period; synchronously with activation (rise) of one of the clock signals CK1 and CK2, the other one of the clock signals CK1 and CK2 is inactivated (falls).
In the shift circuit sc1 in a first stage, an electric potential of the node qf1 rises upon activation of the gate start pulse signal GSP. As a result, the first clock signal CK1 is outputted via the node qo1, and accordingly the gate on-pulse signal g1 is activated. Moreover, in the shift circuit sc2 in a subsequent stage, an electric potential of the node qf2 rises upon activation of the gate on-pulse signal g1. As a result, the second clock signal CK2 is outputted via the node qo2, and accordingly the gate on-pulse signal g2 is activated. This activation of the gate on-pulse signal g2 makes the first clock signal CK1 no longer be outputted via the node qo1 in the shift circuit sc1 but a lower-potential side power supply potential be outputted via the node qo1. Consequently, the gate on-pulse signal g1 is inactivated after being active for a certain period of time, which as a result generates a pulse P1.
That is, in the shift circuit sci (i=2, 3, . . . or m−1), an electric potential of the node qfi rises upon activation of the gate on-pulse signal g(i−1). As a result, the clock signal (CK1 or CK2) is outputted via the node qoi, and accordingly the gate on-pulse signal gi is activated. Moreover, in the shift circuit sc(i+1) in a subsequent stage, an electric potential of the node qf(i+1) rises upon activation of the gate on-pulse signal gi. As a result, the clock signal (CK2 or CK1) is outputted via the node qo(i+1), and accordingly the gate on-pulse signal g(i+1) is activated. This activation of the gate on-pulse signal g(i+1) makes the clock signal no longer be outputted via the node qoi in the shift circuit sci but a lower-potential side power supply potential be outputted via the node qoi. Consequently, the gate on-pulse signal gi is inactivated after being active for a certain period of time, which as a result generates a pulse P1.
Moreover, in the shift circuit scm, an electric potential of the node qfm rises upon activation of the gate on-pulse signal g(m−1). As a result, the clock signal (CK1 or CK2) is outputted via the node qom, and accordingly the gate on-pulse signal gm is activated. Further, in the dummy shift circuit scd in a subsequent stage, an electric potential of the node qfd rises upon activation of the gate on-pulse signal gm. As a result, the clock signal (CK2 or CK1) is outputted via the node qod (i.e., an electric potential at the node qod rises). The rise of the potential of the node qod makes the clock signal no longer be outputted via the node qom in the shift circuit scm, but a lower-potential side power supply potential be outputted via the node qom. Therefore, the gate on-pulse signal gm is inactivated after being active for a certain period of time, which as a result generates a pulse Pm.
As discussed above, in the shift register 100, the gate on pulse signals outputted from respective shift circuits are successively activated for a certain period of time, and a pulse is outputted successively from respective shift circuits in order of ordinal number starting from the shift circuit sc1 in the first stage until the shift circuit scm in an end stage. Note that the following Patent Literatures 1 through 3 are known documents relevant to the technique described above.
Patent Literature 1    Japanese Patent Application Publication, Tokukai, No. 2001-273785 A (Publication Date: Oct. 5, 2001)
Patent Literature 2    Japanese Patent Application Publication, Tokukai, No. 2006-24350 A (Publication Date: Jan. 26, 2006)
Patent Literature 3    Japanese Patent Application Publication, Tokukai, No. 2007-114771 A (Publication Date: May 10, 2007)